Advanced CMOS Technology (The 28/22/15nm Nodes)

The course has been newly updated to include all of the latest developments in FinFet fabrication and is technically current through May 2013.

Course Description:

The relentless drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 22 nm node and ushered in a new era of 3-dimensional transistor structures. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing challenges that require revolutionary new process methodologies as well as innovative, new equipment for the 22 nm and 15 nm nodes. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 28 nm half-node technology, as well as previews the upcoming manufacturing issues of the 22/15 nm nodes.

The central theme of this seminar is an in-depth presentation of the key 28/22/15 nm node technical issues: CD control, electrical leakage mitigation, high-k/metal gate integration, ultra-shallow junctions implementation, immersion lithography, mobility enhancement, Copper/low-k integration and FinFet, Flash and DRAM process integration. Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue.

Date: To Be Announced
Location: To Be Announced
Tuition: $1,895 

What’s Included:

• Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
• A high quality set of full-color lecture notes (a $495 value), including SEM & TEM micrographs of real- world IC structures that illustrate key points
• Continental breakfast, hot buffet lunch, and coffee, beverages, & snacks served at both morning and afternoon breaks

Who is the seminar intended for:

• Process Development & Process Integration Engineers & Scientists
• Process Equipment Marketing, Applications, & Product Development Managers, Engineers, & Scientists
• Materials Supplier Marketing, Applications, & Product Development Managers, Engineers, & Scientists
• Fabless Design Engineers and Managers; Foundary Interface Engineers and Managers
• Process Engineers & Scientists
• Device Engineers & Scientists
• Semiconductor Manufacturing Engineers & Managers
• IC Product Engineering or Marketing Personnel
• VLSI Design Engineers

Course Topics:

1. 28nm Technology. The 28nm technology node represents a landmark in semiconductor manufacturing. It enables a substantial reduction in chip area compared to the 32nm node, and employs transistors that are substantially faster than anything ever previously fabricated. The 22/15 nm nodes will continue this performance trend. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling issues, as well as the introduction of radical new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 28nm half-node and describes the key technical issues that had to be resolved in order to make the 22/15nm nodes a reality.

• Technology node definition
• The promise of 28nm applications
• Technical roadblocks: problems and solutions
• Unique 28/22/15 nm manufacturing challenges

2. Detailed 28nm Fabrication Sequence. The key to rapidly understanding any new technology is to view it in its entirety. This approach provides a context and a perspective that the study of isolated technical components cannot. Once a sense of technical perspective is established, the student can "drill-down" into each technical area of interest and expand their understanding of the subject matter. This portion of the seminar presents a detailed 28 nm Logic process flow from beginning-to-end (FEOL & BEOL). The underlying purpose of each process step will be explained and the processing options and equipment considerations in each major process module are highlighted. The purpose of this section of the course is to establish a baseline understanding of this new technology node and to provide a fundamental framework for the subsequent in-depth presentations on each technical issue. It includes:

• A detailed step-by-step 28nm fabrication process flow
• Front End Of Line (FEOL) processing options and technical considerations (new Hi-K dielectric & metal gate, strain, and salicide integration techniques)
• Gate-first and Gate-Last integration methodologies
• Back End Of Line (BEOL) processing details (copper metallization, low-k dielectric, and barrier layer integration)
• The underlying purpose of each processing operation is discussed and the processing options and equipment considerations for each major module presented

3. Flash & DRAM device module-processing sequences. Logic processing often receives the most attention but this perspective overlooks the critical role played by DRAM, and increasingly, the ever-expanding role played by Flash technology. This section of the course describes in detail the device module fabrication sequence for these two important technologies, highlighting the key processing advances that have been made, and the processing issues remaining to be resolved for future technology nodes.

• Detailed step-by-step fabrication sequence for both the Flash and DRAM device modules
• The purpose of each processing step and the fabrication methodology used for each operation are explained in detail
• 3D packaging considerations and options are also presented

4. FinFet Process Integration. The FinFet represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. This section of the course drills down into the details of FinFet structure and fabrication, highlighting the novel manufacturing issues this new type of transistor presents.

• A detailed step-by-step description of how a FinFet process can be integrated into a CMOS process flow
• Key fabrication details of FinFet manufacturing

5. CMOS Devices Logic (high-performance, low-power, ultra-low power), Memory (DRAM, SRAM, Flash). The electrical performance of CMOS devices & ICs is fundamentally determined by the CMOS physical structure (e.g., gate length), the 3D activated dopant profiles within the device, and the materials of construction employed for the device & contacts. This course will provide detailed descriptions and striking pictures of state-of-the-art CMOS devices for Logic (high performance, low power, & ultra-low power) and Memory (DRAM, SRAM, Flash).

• Brief but technically comprehensive overview of CMOS device structure, function, and materials of construction for all these applications
• In-depth discussion of all key scaling and functional integration issues for all the applications
• Detailed device structure and technology roadmaps for all CMOS device applications

6. Controlling sensitivity to process variation. Leading-edge (28/22/15nm) CMOS device technology is very sensitive to fab process and device layout/design variations. This section of the seminar provides a crisp review of the root cause of the increasing electrical performance sensitivity in CMOS devices to processing and design layout variations at 28/22/15nm. It will also explain the leading-edge fab process and IC layout/design techniques that are required to control and reduce these yield-killing variations.

• Root causes of CMOS sensitivity to fab process and layout variations
• Detailed discussion of all traditional sources of variation (e.g., gate CD, other fab processes)
• Comprehensive explanation of new &dbquo;CMOS nanotechnology&dbquo; variations
• Processing & layout/design techniques that control or even reduce variation in state-of-the-art CMOS

7. Controlling leakage and power dissipation. Leakage and active power dissipation have become "show-stopping" issues for further scaling of CMOS ICs. The challenge of device leakage and circuit power dissipation is so severe that both process and design solutions at the device level and circuit level design techniques are required in combination to effectively address the problem. This section of the seminar will: 1) describe all sources of device leakage and power dissipation, 2) describe the CMOS processing and design techniques that are employed to minimize leakage for low and ultra-low power logic and memory applications, and 3) identify and describe the most effective device and circuit level power management techniques that are employed at 28/22/15nm to mitigate device leakage/IC power dissipation.

• Leakage suppression techniques for subthreshold, junction, & gate
  dielectric leakage
• Power management techniques for active & passive power dissipation
• Impact of device architecture (FinFETs, other 3D devices)

8. New fab process modules and process control issues for 28/22/15nm. Double patterning lithography creates challenges for lithography & etch process control and advanced ultra-shallow junction (USJ) formation techniques create challenges for implant & thermal processes that directly impact fundamental CMOS device performance.

• Double patterning lithography: litho & etch process control issues
• Advanced USJ formation: implant & thermal process control issues
• New sources of process sensitivity/yield impact and appropriate mitigation techniques

9. State-of-the-art CMOS performance boosters (mobility enhancement techniques). Conventional device performance scaling requires reducing the thickness of the gate oxide to increase the channel inversion charge density, which increases device drive current. However, gate oxide thickness scaling has been stalled at ~12 due to rapidly increasing leakage (tunneling) as the gate oxide dielectric thickness is reduced. Also, as the device structure is scaled, device parasitic resistance is increasing and is robbing a significant fraction of the device performance increase (drive current) we expect with scaling. Alternate methods of increasing device performance (drive current) must be employed to compensate for this shortfall. Mobility enhancement technologies (strain, new channel orientations) are aggressively stepping forward to fill this requirement and are being widely implemented in 28/22/15nm fabrication processes. It is now clear that mobility enhancement technologies will be employed for all CMOS nodes through the end of the technology roadmap.

This section of the seminar will explain how mobility enhancement technologies work to improve mobility, drive current, and device performance. It will identify and describe all leading-edge mobility enhancement technologies and explain the details of how they are integrated into a CMOS manufacturing flow.

• Leading-edge uniaxial tensile (NMOS) and compressive (PMOS) strain techniques
• Optimized channel orientation for NMOS & PMOS
• Which mobility enhancement techniques work with FinFETs?

10. Lithography update: status and roadmap. The most important, fundamentally enabling technology for implementation of 28/22/15nmnode CMOS technology is the lithographic process capable of creating photoresist lines and spaces of appropriately small dimensions with adequate precision and reproducibility. 193nm immersion lithography technology, combined with double patterning lithography techniques, has stepped into this role. This section of the seminar will provide in-depth discussion of the current status and future prospects for 193i optical lithography for 28/22/15nm node high-volume CMOS manufacturing.

• Current status and future prospects for optical lithography
• Double patterning lithography techniques
• Future alternatives to optical lithography

11. 3D Packaging. Unlike all other forms of advanced packaging that communicate by routing signals off the chip (as if they were mounted on a traditional circuit board), 3D packaging permits multiple chips to be layered one on top of each other, and to communicate with each other using on-chip signaling, as if they were all one unified microchip. This methodology promises to create a revolution in not only the way microchips are packaged, but also in the functionality, performance and the design of electronic systems. In addition, this architecture dramatically lowers the package footprint, reduces power consumption and reduces propagation delay resulting in increased system speed.

This part of the course identifies the underlying technological forces that have driven the development of 3D technology, the different types of 3D packages, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of this technology.

• The role of interposers in 3D packaging design
• Thru-Silicon Technology: design, processing and production
• TSV formation: barrier & seed fill
• TSV fill & CMP
• Can 3D packaging be made cost effective?
• The key technical hurdles to the widespread adoption of 3D technology
• A timeline for 3D packaging implementation

12. 15/11/8nm CMOS roadmap and device technology forecast. Ultimately, all good things must some to an end, and the end of classical (bulk, planar) CMOS is, if not at hand, at least within sight. No discussion of advanced CMOS technology is complete without a peek into the future. This final section of the course looks ahead to the 15/11/8nm CMOS nodes and forecasts the evolution of CMOS device technology for all CMOS logic and memory applications.

• The end of bulk, planar CMOS is in sight – transition to 3D devices & ICs
• Key technology forecast issues and &dbquo;nanoscale&dbquo; effects - impact on CMOS device architecture/materials
• The two possible paths forward in CMOS device architecture

The Instructors:

Jerry Healey

Jerry Healey has been a technical professional in the semiconductor industry for over 20 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on advanced technology node development.

He is a renowned lecturer in the field of silicon processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, embedded non-volatile memory processing, and mixed signal devices. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful color graphics he uses to illustrate his lectures.

An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 15 years. He has also authored numerous papers in the field of silicon processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.

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Robert Simonton

Robert Simonton is a widely recognized authority in the subjects of leading-edge CMOS front-end-of-line (FEOL) process integration trends and ion implantation process technology. With over thirty years experience in CMOS device and fabrication technology, Mr. Simonton brings unusual breadth and depth to his lecture topics.

Before 2000, Mr. Simonton has held senior product engineering, advanced product/process development, strategic marketing, and CMOS technology forecasting positions with leading semiconductor process equipment companies such as Varian and Eaton. In January 2000, Mr. Simonton founded Simonton Associates, a semiconductor technology consulting and educational services firm that specializes in resolving high-level product/technology development, technology/marketing management, and IP issues for leading-edge semiconductor IC fabrication companies, process equipment suppliers, and materials suppliers. His consulting and research activities keep him in close touch with key challenges and solutions at each new CMOS technology node.

Mr. Simonton has authored and co-authored over 40 technical papers and four book chapters on semiconductor process technology, and is a recipient of the SRC Outstanding Industrial Mentor Award. He has been a popular lecturer in the field of advanced silicon processing for over 15 years. His audiences remember him for his technical depth, broad industry experience, and his engaging, high-energy lecture style.