Lithography for Nano-Technology CMOS ICs
This one-day course describes the state-of-the-art and latest advances in lithography for today’s most advanced CMOS nanotechnology ICs.
This course provides a broad, deep treatment of lithography, the key driver technology in CMOS IC fabrication. It covers all critical lithographic technology elements, from basic concepts to leading-edge technology and applications issues for today’s most advanced CMOS nanotechnology ICs. It will describe the variations in lithographic technology and circuit layout design techniques that are required to optimize performance and control variation in different IC applications for logic and memory. This course is appropriate for professional development of process engineers, applications engineers, device engineers, VLSI design engineers, technical marketing engineers and managers, and process equipment engineers and scientists who wish to improve their understanding of lithography for nanotechnology CMOS ICs. The material is presented using intuitive visual illustrations linked to relevant physics equations, supported by state-of-the-art 2D & 3D graphics and numerous SEM and TEM photographs of real-world, leading-edge CMOS lithographic structures. Key references are provided for independent follow-up studies.
The course begins with a crisp overview of all lithography technology elements and basic concepts. It then describes in detail all leading-edge advances and issues in photoresist masks, resolution enhancement techniques (RET), and exposure tools (steppers, scanners). It has in-depth treatment of the latest advances in double patterning technologies, computational lithography, and design for manufacturability (DFM) techniques. The latest techniques to optimize IC performance and control manufacturing variation for different IC applications (HP logic, SRAM, DRAM & Flash) are explained.
Download this seminar brochure as a .pdf file
Date: To Be Announced
Location: To Be Announced
- A full day of instruction by an industry expert with an in-depth understanding of the course material.
- A high quality set of course notes that are in full color.
- Continental breakfast, hot buffet lunch and snacks at the morning and afternoon breaks.
- Lithography for CMOS nanotechnology ICs – equipment & process
- Overview of lithographic technology elements & review of basic process and equipment concepts
- Stepper and scanner exposure technologies
- Deep UV chemically amplified resist technology and applications issues
- Resolution/throughput/CD control trade-offs, contrast, substrate reflectivity control, etch resistance, line edge roughness (LER), pattern collapse, process variation
- Sub-wavelength lithography with resolution enhancement techniques (RET)
- Sub-wavelength lithography gap & technology roadmap through 22nm-
- RET: customized illumination, optical proximity correction (OPC) and sub-resolution assist features (SRAFs), phase shift masks, double exposure techniques, photoresist feature shrink techniques
- Design for manufacturability (DFM) techniques to control manufacturing variations in logic and memory ICs
- Immersion lithography technology – the latest 193nm optical lithography
- Double patterning technologies – the path to 22nm
- Computational lithography technology – how it extends 193nm optical lithography