The 3D Packaging Revolution
The course has been newly updated to include all of the latest developments in 3D packaging and is technically current through May 2013.
The next significant advancement of Moore's Law is being driven by packaging technology and not transistor evolution. Unlike all other forms of advanced packaging that communicate by routing signals off the chip (as if they were mounted on a traditional circuit board), 3D packaging permits multiple chips to be layered one on top of each other, and to communicate with each other using on-chip signaling, as if they were all one unified microchip. This methodology promises to create a revolution in not only the way microchips are packaged, but also in the functionality, performance and the design of electronic systems. In addition, this architecture dramatically lowers the package footprint, reduces power consumption and reduces propagation delay resulting in increased system speed.
This course identifies the underlying technological forces that have driven the development of 3D technology, the different types of 3D packages, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of this technology.
The course information is introductory in nature and is intended for the busy professional who is interested in learning more about this important, new technology. The course notes are profusely illustrated, and presented in a clear, technically current and easy-to-understand manner. It is intended for product and packaging engineers as well as managers and other personnel who have an interest in 3D packaging technology.
Download this seminar brochure as a .pdf file
Date: To Be Announced
Location: To Be Announced
- A full day of instruction by an industry expert with an in-depth understanding of the course material.
- A high quality set of course notes that are in full color.
- Continental breakfast, hot buffet lunch and snacks at the morning and afternoon breaks.
Who is the seminar intended for:
- Packaging Engineers & Process Integration Engineers & Scientists
- Product Development Managers, Engineers, & Scientists
- IC Product Engineering or Marketing Personnel
- Materials Supplier Marketing, Applications, & Product Development Managers, Engineers, & Scientists
- Fabless Design Engineers and Managers; Foundary Interface Engineers and Managers
- Process Engineers & Scientists
- Device Engineers & Scientists
- Semiconductor Manufacturing Engineers & Managers
- VLSI Design Engineers
- Introduction to 3D Technology
- 3D Market Drivers
- 3D technology for System Applications
- The role of interposers in 3D packaging design
- Thru-Silicon Technology: design, processing and production
- TSV formation: barrier & seed fill
- TSV fill & CMP
- The impact of interposers on mechanical and thermal performance
- Thermal analysis of 3D Applications & hot spot mitigation
- CAD Tools and Design Flows for 3D Applications
- Design for test issues
- Can 3D packaging be made cost effective?
- 3D Integration for Wireless Applications
- Moore's Law and 3D Integration
- Direct Bonding Interconnect technology
- Wafer Level Stacking
- Thin Wafer handling and chip stacking methods
- The key technical hurdles to the widespread adoption of 3D technology
- A timeline for 3D packaging implementation
Jerry Healey has been a technical professional in the semiconductor industry for over 20 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on advanced technology node development.
He is a renowned lecturer in the field of silicon processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, embedded non-volatile memory processing, and mixed signal devices. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful color graphics he uses to illustrate his lectures.
An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 15 years. He has also authored numerous papers in the field of silicon processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.