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The course has been newly updated to include all of the latest
developments in CMOS processing:

Advanced CMOS Technology (The 45/32/22 nm Nodes)

The relentless drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has brought the industry to the 45 nm technology node. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing chal-lenges that require revolutionary new process methodologies as well as innovative, new equipment for the 32 nm and 22 nm nodes. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 45 nm node technology, as well as previews the upcoming manufacturing issues of the 32/22 nm nodes.

The central theme of this seminar is an in-depth presentation of the key 45/32/22 nm node technical issues: CD control, electrical leakage mitigation, high-k/metal gate integration, ultra-shallow junctions implementation, immersion lithography, mobility enhancement, Copper/low-k integration and other critical processing problems. Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solu-tions and equipment requirements necessary to resolve each issue.

Seminar Fee: * $1,795.00
*A 25% discount is available to companies that send five or more employeeS

Who is the seminar intended for?

September 24,25,26
8:00am - 5:00pm daily

Location:
The seminar will be held at:

Spansion Inc. Auditorium
5204 East Ben White Blvd.,
Austin Texas, 78741

For further Information:
Contact Threshold Systems at: (512) 576-6404

1. 45nm NODE TECHNOLOGY AT-A-GLANCE

The 45nm technology node represents a landmark in semiconductor manufacturing. It enables a 50% reduction in chip area compared to the 65nm node, and employs transistors that are substantially faster than anything ever previously fabricated. The 32/22 nm nodes continue this performance trend. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling issues, as well as the introduction of radical new materials. This section of the course highlights the key changes introduced at the 45nm node and describes the key technical issues that had to be resolved in order to make the 32/22 nm nodes a reality.

• Technology node definition
• The promise of 45nm applications
• Technical roadblocks: problems and solutions
• Unique 45/32/22 nm manufacturing challenges
  

2. DETAILED 45/32 nm NODE PROCESS FLOW

The key to rapidly understanding any new technology is to view it in its entirety. This approach provides a context and a perspective that the study of isolated technical components cannot. Once a sense of technical perspective is established, the student can "drill-down" into each technical area of interest and expand their understanding of the subject matter.
This portion of the seminar presents a detailed 45/32 nm process flow from beginning-to-end (FEOL & BEOL). The underlying purpose of each process step will be explained and the processing options and equipment considerations in each major process module are highlighted. The purpose of this section of the course is to establish a baseline understanding of this new technology node and to provide a fundamental framework for the subsequent in-depth presentations on each technical issue. It includes:

• A detailed step-by-step 45/32nm fabrication process flow
• Front End Of Line (FEOL) processing options and technical considerations (new Hi-K o dielectric & metal gate, strain, and salicide integration techniques)
• Back End Of Line (BEOL) processing details (copper metallization, low-k dielectric, and barrier layer integration)
• The underlying purpose of each processing operation is discussed and the processing options and equipment considerations for each major module presented
  

3. WHY IS 45/32/22 nm DEVICE TECHNOLOGY SO SENSITIVE TO FABRICATION PROCESS VARIATIONS? WHAT TECHNIQUES ARE EFFECTIVE AT CONTROLLING THESE VARIATIONS?

_The electrical performance of CMOS devices is fundamentally determined by physical structure, e.g., the gate length and 3D activated dopant profiles within the device. Gate lithography, etch, and implant/anneal processing variations directly impact this fundamental device structure. Consequently, they are the primary source of device performance variation and can also contribute to low yield. This section of the seminar provides a crisp review of the root cause of the increasing electrical performance sensitivity in CMOS devices to processing variations at 45/32/22 nm. It will also explain the key device electrical performance factors that primarily impact the performance quality (speed, power dissipation, etc.) of digital integrated circuits. This section will provide an intuitive conceptual linkage between of device physical structure, manufacturing process variation, and final IC circuit performance quality.

• Primary source of device sensitivity to fabrication process variation – short channel effects (SCE)
• Impact of gate CD variation on Ion, Ioff, and Vt
• New sources of variation at the 45/32/22 nm nodes
• Impact of device parameter variation on IC performance and yield
• Overview of fabrication process variation control techniques

4. THE KEY CMOS PROBLEM: LEAKAGE AND POWER DISSIPATION. HOW CAN ELECTRICAL LEAKAGE BE REDUCED? HOW IS POWER MANAGEMENT ACCOMPLISHED?

Leakage and active power dissipation have become "show-stopping" issues for further scaling of CMOS ICs. The challenge of device leakage and circuit power dissipation is so severe that design solutions at both the device and circuit level are required to effectively address the problem. This section of the seminar describes the sources of device leakage and active power dissipation. It will discuss the most effective device and circuit level techniques that are employed at 45nm to mitigate the rapidly increasing device leakage and power dissipation problems. These techniques will be refined and used again at the 45/32 nm nodes.

• Primary source of device leakage: subthreshold, gate dielectric, & junction leakage
• Leakage suppression techniques - implications for process integration
• Active power dissipation issues: parasitic capacitance and resistance
• Power management techniques: multiple Vt devices, sleep mode devices, back-gate bias, multi-core processors - implications for process integration

5. KEY 45/32/22 nm MANUFACTURING ISSUES: LITHOGRAPHY, ETCH, AND IMPLANT PROCESS CONTROL ISSUES

Gate lithography, etch, and implant/anneal processing variations are the primary sources of device performance variation. New process control techniques must be implemented in order to achieve adequate yield at 45/32/22 nm nodes. This section of the course will drill down into the key 45nm manufacturing process control issues and describe the range of new manufacturing techniques and equipment features that are required to adequately control lithography, etch, and implant process variations for acceptable yields in 45nm node fabrication and beyond.

• Lithography and etch process control issues: poly-gate, contact holes, and metal 1 CD process control and yield issues
• New issues in process control: emerging sources of process sensitivity in implant and anneal processes -impact on yield

6. POLYSILICON GATE "CRITICAL DIMENSION" (CD) CONTROL AT THE 45/32/22 nm NODE - HOW DO FEED FORWARD/FEED BACK AUTOMATED PROCESS CONTROL (APC) TECHNIQUES WORK?

The heart of a microchip is the transistor, and the key performance-limiting component of the transistor is the length of the gate electrode. Defining and consistently maintaining the critical dimension (CD) of this fundamental structure is the most challenging aspect of 45/32/22 nm node manufacturing. This section of the seminar provides a detailed description of the feed forward/feed back manufacturing methodology required to maintain effective control of the polysilicon gate CD. The physical obstacles to effective CD control (193 resist line-edge roughness, etch chamber matching irregularities, top-down CD measurement, etc.) are discussed and quantified.

• The technical challenges in fabricating well-controlled 45/32/22 nm gates
• The adverse impact of poly CD variation
• Identifying and controlling sources of polysilicon gate etch variation
• Using APC with in-line SEM measurement to optimize etch process and control polysilicon gate CD

7. STATE-OF-THE-ART ULTRA-SHALLOW JUNCTION FORMATION: NEW IMPLANT AND ANNEAL TECHNOLOGIES

Ion implantation and associated thermal processes have dramatically evolved to accommodate the ultra-shallow junction formation and polysilicon gate doping requirements for scaling CMOS transistors to the 45/32/22 nm technology nodes. This has resulted in significant changes to both ion implantation and thermal processes and process equipment. This section of the seminar will describe the key developments in ion implantation processing, associated thermal processing, and integration strategies that enable CMOS transistor structure scaling to the 45/32/22 nm nodes. The course identifies the unit process, process equipment and process integration changes that have enabled this scaling. It will explain how these new ion implantation and thermal processes enable the desired device structures and electrical functions.

• New junction implant processes: PAI, co-implants, new species
• New junction implant technologies: plasma doping, high mass molecules
• New junction anneal technologies: Flash, laser
• New junction integration techniques

8. FABRICATION METHOLOGIES FOR METAL GATES AND HI-K DIELECTRICS

Next to the polysilicon gate electrode length dimension, the most important scaling lever in CMOS technology is the thickness of the gate dielectric. However, the inability of silicon dioxide to scale to dimensions thinner than 12Å has posed a seemingly insurmountable roadblock to enhancing transistor drive current via the time-established technique of gate oxide thickness scaling. In addition, ultra-thin silicon dioxide gate oxides exhibit excessive electrical leakage that results in high standby power consumption and imposes severe constraints on IC performance. The solution to this vexing scaling problem lies in the successful employment of gate dielectrics with a k-value that is substantially higher than that of silicon dioxide. Such dielectrics, when employed with metal gates of the appropriate type, are the key enabling technology required to scale to the 45/32/22 nm nodes.
This section of the seminar discusses the problems associated with the development of High-k/metal gate technology, what the technology consists of, and why it works.

• The death of SiO2 gate dielectrics and the driving forces behind the move to Hi-k gate dielectrics
• Issues with Hi-k dielectrics -mobility degradation and the role of interfacial layers
• Fermi-level pinning and the purpose of metal gates
• Metal gate material selection issues and process integration choices

9. THE ROLE OF IMMERSION LITHOGRAPHY AT THE 45/32/22 nm NODES

The most important, fundamentally enabling technology for implementation of 45nm node CMOS technology is a lithographic process capable of creating photoresist lines and spaces of appropriately small dimensions with adequate precision and reproducibility. Recently, immersion lithography technology has stepped into this role ahead of other alternatives for 45nm, however, not everyone will use immersion lithography at 45nm.
This section of the seminar will discuss the fundamental challenges and issues for 45nm lithography technology. It will describe the status and outlook and future development path for immersion lithography at 45/32/22 nm nodes. It will also describe and discuss the alternatives to immersion lithography that will be implemented at the 45nm node and beyond.

• Lithography challenges at 45nm and beyond
• Immersion lithography – status and outlook
• Alternatives to immersion lithography at 45nm and beyond
  

10. NEW CU & LOW-K DIELECTRIC BACK-END INTERCONNECT TECHNOLOGY

So much attention is paid to Front-End of Line (FEOL) processing issues (transistor structure fabrication and process control) that it can be easy to forget that Back End of Line (BEOL) interconnect structures that also determine IC speed, functional complexity, and performance quality. At 45nm, more than at any time in the past, variation in BEOL processing negatively impacts overall chip performance and yield. The aggressively scaled dimensions of metal lines and vias at the 32/22 nm nodes require that special attention be paid to Dual Damascene execution methodology, barrier definition, end-point detection, via-fill, and copper CMP. In addition, the advent of a new generation of low-k dielectrics has presented a host of new integration and manufacturing considerations. This section of the seminar will provide a detailed drill-down on all these BEOL issues.

• Overview of 45/32/22 nm Back End Of Line (BEOL) issues and yield vulnerabilities
• 45nm interconnect physical structure and electrical function
• Local vs. global interconnect structures
• Special considerations for scaled vias and contacts
• Effects of scaling on Cu resistance
• Low-k dielectric considerations and process integration issue

11. MOBILITY ENHANCEMENT TECHNOLOGY - UNIAXIAL STRAIN, CHANNEL ORIENTATION (E.G., HOT)

Conventional device performance scaling requires reducing the thickness of the gate oxide to increase the channel inversion charge density, which increases device drive current. However, gate oxide thickness scaling has been stalled at ~12Å due to rapidly increasing leakage (tunneling) as the gate oxide dielectric thickness is reduced. Also, as the device structure is scaled, device parasitic resistance is increasing and is robbing a significant fraction of the device performance increase (drive current) we expect with scaling. Alternate methods of increasing device performance (drive current) must be employed to compensate for this shortfall. Mobility enhancement technologies (strain, new channel orientations) are stepping forward to fill this requirement and are being aggressively implemented in fabrication processes. It is now clear that mobility enhancement technologies will be employed not only at 45nm, but also for all planar CMOS nodes through the end of the technology roadmap. This section of the seminar will explain how mobility enhancement technologies work to improve mobility, drive current, and device performance. It will identify and describe all mobility enhancement technologies likely to be implemented at 45nm and beyond. It will also describe the details of how they are integrated into a CMOS manufacturing flow.

• How does strain work to improve carrier mobility and drive current?
• Sources of compressive and tensile uniaxial strain: nitride films, silicon lattice mismatch (etch with SiGe or SiC deposition/refill), STI & salicide process-induced strain, and "memorization" strain
• Uniaxial strain integration techniques
• Channel orientation effects and hybrid orientation technology (HOT)

12. OVERVIEW OF 32/22 nm CMOS TECHNOLOGY; ISSUES AND CHALLENGES

Ultimately, all good things must some to an end, and the end of classical CMOS has been predicted for at least the last two decades. Despite these dire predictions, the technology not only persists, it thrives. However, there is no avoiding the reality that with gate electrode dimensions of ~12nm and channel lengths well under 100 atoms in length, the end of classical CMOS if not at hand, is at least within sight. No discussion of 45nm node technology is complete without a peek into the future of the next two generations, the 32 nm and 22 nm nodes. This final section of the course looks ahead to the 32/22 nm nodes and explores the technical problems that these generations of devices present, as well as probable solutions.

• Is 22nm the terminal point for classical (planar) CMOS and Moore’s law?
• Nanoscale effects and their growing impact on CMOS manufacturing
• Lithography technology for 32/22 nm
• 32/22 nm device design & manufacturing issues and probable solutions

The Course Instructors:

The best instructors in the business will be teaching this course. Each instructor is a world-class expert in their respective field, with decades of industry experience. However, Threshold Systems has selected these presenters not just for their deep technical expertise, but also for their ability to present complex technical information in a clear and engaging manner. Each of these instructors is an experienced and skilled public speaker, and the accompanying course notes for this seminar are profusely illustrated with relevant graphics. It is our intention for you to leave this course with a clear understanding of the key enabling technologies that are revolutionizing semiconductor manufacturing.

Jerry Healey

JERRY HEALEY BIOGRAPHY

Jerry Healey has been a technical professional in the semiconductor industry for 19 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on 45 nm node development.

He is a renowned lecturer in the field of Silicon Processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, embedded non-volatile memory processing, and mixed signal devices. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful color graphics he uses to illustrate his lectures.

An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 10 years. He has also co-authored over 20 papers in the field of Silicon Processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.

“"Jerry Healey is a superb public speaker who has a knack for making complex technical subjects seem clear and understandable.”" - J. Blume, AMD

Robert Simonton

ROBERT SIMONTON BIOGRAPHY

Robert Simonton is a world-recognized authority in the subjects of ion implantation process technology, rapid thermal processing, and leading-edge front-end-of-line (FEOL) process integration. Mr. Simonton has extensive experience in the semiconductor industry; he has been a technology professional in the industry for nearly thirty years. During this period he has held a wide range of high-level technical positions that have afforded him the opportunity to develop a very broad and deep understanding of semiconductor processing issues.

Before 2000, Mr. Simonton has held a variety of senior product engineering, advanced product/process development, strategic marketing, and technology management positions with leading semiconductor process equipment companies such as Varian and Eaton. In 2000, Mr. Simonton founded Simonton Associates, a consulting firm that specializes in resolving high-level technology and management issues for leading semiconductor suppliers.

He has authored and co-authored over 40 technical papers and four book chapters on semiconductor process technology, and is the recipient of the SRC Outstanding Industrial Mentor Award.

Mr. Simonton has been a popular lecturer in the field of advance silicon processing for over a decade. His audiences remember him best for his technical depth, his broad industry experience, and his engaging, high-energy lecture style.

“"Mr. Simonton is a walking encyclopedia of information regarding semiconductor processing issues. His knowledge is both current and leading edge. I really enjoyed his talk immensely.”"
- T. Jamison, Intel