A new one day course that examines the effect of typical silicon processing variations on final electrical parametrics and device yield in CMOS IC technology.

Course Description:

The objective of this one-day course is to provide a thorough, intermediate level treatment of semiconductor device and interconnect structure and function, and to identify the effect of typical processing variations on the electrical function of these structures. The course content is current and rich in technical detail. This course is appropriate for professional development of engineers (process engineers, device engineers, product engineers, failure analysis engineers, VLSI design engineers, process development engineers, yield and reliability engineers), scientists, and senior technicians with some semiconductor manufacturing or design experience (1-5 years, or more). It is intended for those persons who wish to broaden and deepen their understanding of semiconductor device structure and function and the effect on device electrical parameters of typical processing variations encountered in real-world silicon wafer fabrication.

The material is presented using intuitive visual models linked to relevant physics equations, supported by state-of-the-art, 2D and 3D color graphics and numerous SEM and TEM photographs of leading edge semiconductor device structures. The class is highly interactive, with in-class exercises employing relevant case studies to illustrate key device performance and processing interactions. The course builds an intuitive link between process steps, device structure, and device performance. The case studies reinforce this linkage. The lectures will highlight those aspects of the topics most relevant for the real world of high-yield commercial integrated circuit manufacturing.

The lectures describe leading-edge CMOS devices and interconnect structures, explain their electrical functions, and identify how typical fabrication process variations cause variations in electrical performance. The course begins with a review of necessary basic material in CMOS device operation and silicon materials physics to facilitate comprehension of the more advanced topics in the course, which describe the effect on CMOS device performance of processing variations in a modern semiconductor fabrication environment. The course describes the key electrical parameters used to characterize CMOS device and circuit performance, and identifies the linkage of electrical performance to device and circuit structure. It describes typical parametric test information, and identifies the linkage between electrical test parameter variations, device structure variations, and processing variations. Typical, mainstream silicon fabrication process sequences are reviewed and advanced, leading edge process integration strategies are identified and discussed.

Course Topics:

• Review of semiconductor physics and silicon materials science - semiconductor band gap, intrinsic and extrinsic carriers, doping, carrier action, mobility degradation, velocity saturation

• Review of P-N junctions and MOS capacitors: structure and function

  • P-N junctions: I-V characteristics, depletion widths, forward and reverse bias electron and hole currents (drift and diffusion), impact ionization (avalanche breakdown, hot carrier generation), generation and recombination mechanisms, leakage current mechanisms, ideal vs real world behaviors – sensitivity to processing and contamination

  • MOS capacitor: C-V characteristics, accumulation, depletion, and inversion (threshold voltage) – sensitivity to processing and contamination

• CMOS devices: structure and function

  • Physical structure of real devices, both basic and leading edge (aggressively scaled) transistors

  • Electrical function - key characteristics critical to real commercial devices

  • CMOS: I-V characteristics, threshold voltage, saturation (drive) current (I_on), sub-threshold (off) current (I_off, leakage), punchthrough, DIBL, sub-threshold slope, hot carrier effects, GIDL, parasitic capacitances and resistances, transistor leakage mechanisms – sensitivity to processing variations

  • Parasitic devices within and around CMOS transistors: parasitic diodes (capacitance), MOS field transistors (inter- and intra-well field inversion), parasitic bipolar structures (latch-up)

• Electrical characterization and diagnostics for CMOS (transistor I-V curves, C-V analysis, gate oxide testing, interpretation of SEMs and TEMs)

• CMOS device performance and process interactions – linkage of typical processing variations to electrical performance

• CMOS performance factors for digital ICs - role of structure and processing variation in circuit delay (speed), active power dissipation, standby power dissipation, reliability

  • Deep sub-micron CMOS scaling – tradeoffs (performance, power dissipation), technology barriers

• CMOS device applications - differences in device structure, function, and process execution for high performance logic, low power logic, SRAM, and non-volatile memory devices

• Interconnect structure and function: conductors and insulators (dielectrics)

  • Structure and functional role of IC interconnects: local vs system (global) level interconnects, metal lines, vias, silicon contacts

  • Structure and functional role of IC to package interconnects

  • Physics of interconnects: resistivity, contact resistance, Ohmic contacts, Schottky barriers, dielectric constant, capacitance – highlight relevance to real world ICs
    

  • Parasitic resistance and capacitance (inter-layer vs intra-layer capacitance)

  • R-C delays in global interconnects – effect on IC performance

• Interconnect materials properties

  • Typical interconnect materials and relevant physical properties
    

    • Conductors (Al, Cu) – resistivity, physical properties, sensitivity to processing variation

    • Dielectrics (SiO₂, BPSG, TEOS, Si₃N₄, low-K materials)

  • Role of physical properties in local interconnect, global interconnect, and package interconnect functions - key materials properties and processing considerations determining the selection of specific materials for particular functional interconnect roles

• Interconnect scaling: trends in IC and package interconnects

  • Fundamental motivations – IC performance, increased IC functions, materials properties

  • Implications for processing steps and process integration strategies

• Electrical testing of fabricated wafers - interpretation of typical test information, linkage to device structure and processing variations

COST: $595/Student

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