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CMOS Device-PROCESS Interactions
Seminar Outline

The bulk of the advanced logic IC products that are transforming our work and
play environments are produced using 180nm, 130nm, and 90nm technologies.
As this high volume manufacturing technology progression has occurred, the impact of manufacturing process variations and other yield loss mechanisms have been sharply increasing. This intensive seminar describes the typical, real-world process variations and other yield loss mechanisms encountered in advanced CMOS logic manufacturing, and describes appropriate techniques for addressing the yield impact of these important issues.

The central theme of this seminar is the interpretation of end-of-line electrical failure signatures and the subsequent isolation and identification of the processing variations that cause such yield failures. Front-end-of-line issues (e.g., transistor parameter control) and back-end metallization failure modalities will be covered. Special emphasis will be placed on 90 nm
production issues, although 130 nm and 180 nm manufacturing concerns will
also be discussed.

The full range of active layer process integration issues and their most probable failure modalities will also be presented. In each instance the deductive methodologies employed to trace back to the processing anomaly that is the root cause of the yield failure
will be examined. Actual case studies of real-world 90 nm failure modalities will be
presented, and the strategies utilized to solve them will be discussed in detail.

What's included:

a) three days of instruction
b) A high quality set of course notes ($395 value)
c) Three lunches, morning and afternoon refreshments

Who is the seminar intended for?

• Process Engineers & Scientists
• Device Engineers & Scientists
• Yield & Reliability Enhancement & Failure Analysis Engineers
• Process Development & Processing Integration Engineers & Scientists
• IC Product Engineering or Marketing Personnel
• VLSI Design Engineers
• Semiconductor Manufacturing Engineers & Managers
• Capital Equipment & Materials Suppliers
  

Schedule:

June 4, 5, 6
8:00am - 5:00pm daily

Location:
The seminar will be held at:

San Jose Marriott Hotel,
301 South Market Street
San Jose, California 95113
(408) 280-1300

For further Information:
Contact Threshold Systems at: (512) 576-6404

1. PROBLEM SOLVING METHODOLOGY

Skilled problem diagnosis at the heart of resolving any yield issue. However, it is also perhaps the most confusing and difficult to master. Clearly defining what the problem is (or if it even exists) is at least as difficult as implementing the corrective action required to resolve the problem. Even experienced Process and Device engineers often struggle to isolate and identify the process
variation or defect that precipitates a yield failure. Unfortunately, due to the novelty of the technology that is often involved with silicon processing, and the unique one-of-a-kind nature of yield problems, no universal rules exist. However, there are established guidelines and traditional
approaches that can be useful. This part of the course presents a useful working methodology for efficiently approaching a low yield situation.

• Defining the failure signature
  • Across-the water
  • Across-the-lot
  • Wafer-to-wafers
  • Lot-to-lot
    
    
• Wave failures
  
  
• Formulating a Working Theory
  
  
• The theory/test/revise/test approach
  
  
• The grand slam approach

2. CASE STUDIES

A consistent and meaningful theoretical approach to solving yield problems is essential to success. However, the fastest way to master a complex problem-solving paradigm is to study published examples of similar problems and analyze how they were resolved. Much can be learned from examining what tools were used when and where, and what mistakes were made in the course off isolating and resolving a process variation that resulted in a yield crisis.

In this part of the course, published case studies
of real-world processes failures are presented, as well as the isolation of the failure modality and the resulting corrective action for each failure.

• Contact failures
  
  
• Sillicide failures
  
  
• Transistor failure modalities
  • Poly depletion
  • Boron penetration
    
    
• Poor drive current
  

3. Analytical Tools

How can you solve a problem if you cannot find it?

Modern microchips are the most complex artifacts ever fabricated, and the analytical tools required to troubleshoot them are extremely sophisticated. A major component of any problem solving methodology is the selection of what analytical tool to bring to bear on the problem to generate the fastest, most relevant results. This portion of the course provides an overview of the array of available analytical tools, and provides guidelines for using them in an optimal manner as well as interpreting the results they produce.

• Scanning Electron Microscopy
  
  
• Transmission Electron Microscopy
  
  
• Optical Microscopy
  
  
• Electron Energy Loss Spectroscopy
  
  
• Secondary Ion Mass Spectroscopy
  
  
• Auger analysis
  

4. CMOS Process Flows

In order to understand the sources of process variation and their impact on device yield, an understanding of typical CMOS process flows for the relevant technology nodes is required. This portion of the seminar provides a detailed step-by-step presentation of the processing operations involved in the fabrication of the three high volume technology nodes that are currently dominating semiconductor manufacturing. Each process flow is reviewed from beginning to end, and the critical processing steps that are most vulnerable to process variations are identified and discussed.

• 180 nm process flow
  
  
• 130 nm process flow
  
  
• 90 nm process flow
  
  
• Relative weaknesses and strengths of each generation
  

5. CMOS Devices

This portion of the course provides a crisp review
of leading-edge CMOS device structures and their electrical functions, identifies the key electrical parameters used to characterize CMOS device
and circuit performance, and explains the linkage of electrical performance to device and circuit structure. It will describe typical parametric test information currently employed in high volume manufacturing.

• Key electrical parameters
  
  
• Characterizing CMOS device and circuit performance
  
  
• Linking electrical performance to device and
  circuit structure
  
  
• Typical parametric tests currently employed in
  high volume manufacturing
  
  
• I-V curves/ C-V curves/ Ion/Ioff curves
  
  
• GOI data
  
  
• Trade-offs between desirable and undesirable electrical characteristics
  
  
• Parasitic resistance and capacitance
  
  
• Transistor leakage
  
  
• The impact of device scaling on device structure and electrical function

6. CMOS Performance Factors for Digital ICs

The fundamental determinant of transistor electrical performance is its physical structure (e.g., dopant densities and profiles). Because processing variations strike at the heart of transistor structure, they are frequently the source of underperforming devices and ultimately, low yield.

The section of the course reviews the key electrical performance factors that impact the quality of digital integrated circuits. It then goes on to explain the role of device physical structure and manufacturing process variation on IC circuit performance.

• A review the key electrical performance factors that impact the quality
  of digital integrated circuits
  
  
• The role of device physical structure and manufacturing process variation for:
  • Circuit delay (speed)
  • Active & standby power dissipation
    

7. Variations in CMOS Device Structure, Function and Process Execution

Different classes of microelectronic devices
feature different types of active elements, depending on the role that each element is designed to perform. Each of these elements (transistors, DRAM trench and stacked capacitors, EEPROM and Flash memory cells) have different strengths and vulnerabilities. The section of the course will compare and contrast the differences
in device structure, desired electrical function, and fabrication process execution for the most common types of devices currently in use in high volume manufacturing.

• High performance logic
  
  
• Low power logic
  
  
• DRAMs
  
  
• FLASH memory
  

8. CMOS Performance and Process Interactions

No discussion of CMOS Process-Device interactions is complete without an in-depth examination of the linkage of fundamental manufacturing process drift to specific electrical performance variations. It is insufficient to merely become familiar with predicable parametric variation due to established process drift. The high level of complexity inherent in modern IC manufacturing virtually ensures that novel failure modalities will manifest themselves that are not readily predictable or familiar. In order to address such issues, a deeper understanding of fundamental device structure, desirable performance, and underlying device vulnerabilities is required.

• The linkage of fundamental manufacturing process variations to electrical performance variations
  
  
• Transistor sensitivity to process variation is regard to:
  • Desirable I-V curves
  • Undesirable (parasitic) capacitance and resistance
  • Transistor isolation mechanisms
  • Isolation leakage modalities

9. Back-End Metallization

So much attention is paid to Front-End of Line (FEOL) processing that it is easy to forget that it is the Back End of Line (BEOL) that ultimately determines a chip‚s speed, complexity and ultimately, its performance. Now, more than at any time in the past, variation in BEOL processing will negatively impact overall chip performance and yield. Becoming familiar with BOEL vulnerabilities and knowing how to isolate, identify and control BEOL processing variations is essential to sustaining high-yields on a modern manufacturing line.

• Overview of Back End of Line (BEOL) issues and vulnerabilities
  
  
• Interconnect physical structure and electrical function
  
  
• Roles of interconnect structures and insulators
  
  
• Local vs. global interconnect structures
  
  
• Vias and contacts
  
  
• The effects of scaling on Cu resistance
  
  
• Typical failure modalities
  
  
• Low-k dielectrics considerations and failure modalities
  

The Course Instructors:

The best instructors in the business will be teaching this course. Each instructor is a world-class expert in their respective field, with decades of industry experience. However, Threshold Systems has selected these presenters not just for their deep technical expertise, but also for their ability to present complex technical information in a clear and engaging manner. Each of these instructors is an experienced and skilled public speaker, and the accompanying course notes for this seminar are profusely illustrated with relevant graphics. It is our intention for you to leave this course with a clear understanding of the key enabling technologies that are revolutionizing semiconductor manufacturing.

Jerry Healey

JERRY HEALEY BIOGRAPHY

Jerry Healey has been a technical professional in the semiconductor industry for 19 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on 45 nm node development.

He is a renowned lecturer in the field of Silicon Processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, embedded non-volatile memory processing, and mixed signal devices. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful color graphics he uses to illustrate his lectures.

An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 10 years. He has also co-authored over 20 papers in the field of Silicon Processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.

“"Jerry Healey is a superb public speaker who has a knack for making complex technical subjects seem clear and understandable.”" - J. Blume, AMD

Robert Simonton

ROBERT SIMONTON BIOGRAPHY

Robert Simonton is a world-recognized authority in the subjects of ion implantation process technology, rapid thermal processing, and leading-edge front-end-of-line (FEOL) process integration. Mr. Simonton has extensive experience in the semiconductor industry; he has been a technology professional in the industry for nearly thirty years. During this period he has held a wide range of high-level technical positions that have afforded him the opportunity to develop a very broad and deep understanding of semiconductor processing issues.

Before 2000, Mr. Simonton has held a variety of senior product engineering, advanced product/process development, strategic marketing, and technology management positions with leading semiconductor process equipment companies such as Varian and Eaton. In 2000, Mr. Simonton founded Simonton Associates, a consulting firm that specializes in resolving high-level technology and management issues for leading semiconductor suppliers.

He has authored and co-authored over 40 technical papers and four book chapters on semiconductor process technology, and is the recipient of the SRC Outstanding Industrial Mentor Award.

Mr. Simonton has been a popular lecturer in the field of advance silicon processing for over a decade. His audiences remember him best for his technical depth, his broad industry experience, and his engaging, high-energy lecture style.

“"Mr. Simonton is a walking encyclopedia of information regarding semiconductor processing issues. His knowledge is both current and leading edge. I really enjoyed his talk immensely.”"
- T. Jamison, Intel