The Transition from 28nm to 22nm
The course has been newly updated and is
This one-day class is designed to provide an understanding of the key technical challenges involved in the migration from 28nm node to 22nm node technology and to provide a detailed understanding of the processing differences between 3D and 2D planar devices for each of the different processing modules in a silicon process flow. This is accomplished by conducting a side-by-side comparison of each processing module for Planar versus 3D fabrication methodologies, identifying the key technical differences and similarities of each module, and the critical processing steps and vulnerabilities at each operation.
The entire front-end process flows for both 28nm Planar and 22nm FinFet are examined and contrasted one processing module at a time. Extensive use of high quality 3D graphics and TEMs of real-world devices are used in this examination.
The course content is presented in a clear, highly visual and easy-to-understand manner. It is taught by a world-class instructor who has over 20 years of hands-on experience in the field of silicon fabrication and who is an award winning public speaker.
The course notes are technically current, reproduced in high resolution color and profusely illustrated.
Download this seminar brochure as a .pdf file
Date: To Be Announced
Location: To Be Announced
- A full day of instruction by an industry expert with an in-depth understanding of the course material.
- A high quality set of course notes that are in full color.
- Continental breakfast, hot buffet lunch and snacks at the morning and afternoon breaks.
This course is intended for:
- Device, Test and Process engineers
- Failure analysis engineers
- Equipment engineers
- Fab interface engineers
- Patent Attorneys
- Managers and other personnel who desire a deeper understanding 22nm FinFet processing
Jerry Healey has been a technical professional in the semiconductor industry for over 25 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on advanced technology node development.
He is a renowned lecturer in the field of silicon processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, 3D Packaging and FinFET fabrication. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful 3D color graphics he uses to illustrate his lectures.
An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 15 years. He has also authored numerous papers in the field of silicon processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.
“The change from planar processing to 3D FinFETS was a complete mystery to me until I took this course, but now I have an understanding of this subject. Great course. Terrific graphics!” – I. Chang
“This course provides a clear and easy-to-understand explanation of both planar and 3D silicon processing. I learned a lot and instructor was extremely knowledgeable.” – R. Carroll