Semiconductor Training:

45nm NODE CMOS TECHNOLOGY (AND BEYOND)

The relentless drive in the semiconductor industry for smaller, faster, cheaper integrated circuits has brought the industry to the 45nm technology node. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform our work and leisure environments. However, the implementation of this technology and subsequent technology nodes faces a range of manufacturing challenges that require revolutionary new process technology and methodology, as well as innovative new equipment. This seminar addresses these issues with technical depth and clarity, describing the leading-edge integrated process solutions to the novel problems presented by 45nm technology, and also provides a look ahead to the key challenges presented by scaling beyond 45nm.

The central theme of this seminar is an in-depth description of the key 45nm node technical issues: CD control, electrical leakage mitigation, High-k gate dielectric/metal gate integration, ultra-shallow junction formation with millisecond annealing, immersion lithography, mobility enhancement technology integration, copper metal/low-k ILD integration, and manufacturing process control challenges. Each section of the seminar will present the key technical issues in an accurate, clear, and comprehensible fashion, explaining the fundamentals of each problem and discussing the processing solutions and equipment requirements necessary to resolve each issue.

1. Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material

2. A high quality set of full-color lecture notes (a $395 value), including SEM & TEM micrographs of real-world IC structures that illustrate key points

3. Continental breakfast, hot buffet lunch, and coffee, beverages, & snacks served at both morning and afternoon breaks
   
   

Who is the seminar intended for?

• Process Development & Process Integration Engineers & Scientists
• Process Equipment Marketing, Applications, & Product Development Managers, Engineers, & Scientists
• Materials Supplier Marketing, Applications, & Product Development Managers, Engineers, & Scientists
• Process Engineers & Scientists
• Device Engineers & Scientists
• Semiconductor Manufacturing Engineers & Managers
• IC Product Engineering or Marketing Personnel
• VLSI Design Engineers
• Yield & Reliability Enhancement & Failure Analysis Engineers
  
  

Schedule:

October 29, 30, & 31
8:00am - 5:00pm daily

Location:
The seminar will be held at:

Santa Clara Hilton,
4949 Great American Parkway,
Santa Clara California, 95054
(408) 330-0001

For further Information:
Contact Threshold Systems at: (512) 576-6404

DETAILED CONTENTS OF SEMINAR TOPICS:

1. 45nm NODE TECHNOLOGY AT-A-GLANCE

The 45nm technology node represents a landmark in semiconductor manufacturing. It enables a 50% reduction in chip area compared to the 65nm node, and employs transistors that are substantially faster than anything ever previously fabricated. However this performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling issues, as well as the introduction of radical new materials.
This section of the course highlights the key changes introduced at the 45nm node and describes the key technical issues that had to be resolved in order to make 45nm a reality.

• Technology node definition
• The promise of 45nm applications
• Technical roadblocks: problems and solutions
• Unique 45nm manufacturing challenges

2. DETAILED 45nm NODE PROCESS FLOW

The key to rapidly understanding any new technology is to view it in its entirety. This approach provides a context and a perspective that the study of isolated technical components cannot. Once a sense of technical perspective is established, the student
can "drill-down" into each technical area of interest
and expand their understanding of the subject matter.

This portion of the seminar presents a detailed 45nm process flow from beginning-to-end (FEOL & BEOL). The underlying purpose of each process step will be explained and the processing options and equipment considerations in each major process module are highlighted. The purpose of this section of the course is to establish a baseline understanding of this new technology node and to provide a fundamental framework for the subsequent in-depth presentations on each technical issue. It includes:

• A detailed step-by-step 45nm fabrication process flow
• Front End Of Line (FEOL) processing options and technical considerations (new Hi-K dielectric & metal gate, strain, and salicide integration techniques)
• Back End Of Line (BEOL) processing details (copper metallization, low-k dielectric, and barrier layer integration)
  

3. WHY IS 45nm DEVICE TECHNOLOGY SO SENSITIVE TO FABRICATION PROCESS VARIATIONS? WHAT TECHNIQUES ARE EFFECTIVE AT CONTROLLING THESE VARIATIONS?

The electrical performance of CMOS devices is fundamentally determined by physical structure, e.g., the gate length and 3D activated dopant profiles within the device. Gate lithography, etch, and implant/anneal processing variations directly impact this fundamental device structure. Consequently, they are the primary source of device performance variation and can also contribute to low yield.

This section of the seminar provides a crisp review of the root cause of the increasing electrical performance sensitivity in CMOS devices to processing variations at 45nm and beyond. It will also explain the key device electrical performance factors that primarily impact the performance quality (speed, power dissipation, etc.) of digital integrated circuits. This section will provide an intuitive conceptual linkage between of device physical structure, manufacturing process variation, and final IC circuit performance quality.

• Primary source of device sensitivity to fabrication process variation – short channel effects (SCE)
• Impact of gate CD variation on Ion, Ioff, and Vt
• New sources of variation at 45nm
• Impact of device parameter variation on IC performance and yield
• Overview of fabrication process variation control techniques

Gate lithography, etch, and implant/anneal processing variations are the primary sources of device performance variation. New process control techniques must be implemented in order to achieve adequate yield at 45nm.

This section of the course will drill down into the key 45nm manufacturing process control issues and describe the range of new manufacturing techniques and equipment features that are required to adequately control lithography, etch, and implant process variations for acceptable yields in 45nm node fabrication.

• Lithography and etch process control issues: poly-gate, contact holes, and metal 1 CD process control and yield issues
• New issues in process control: emerging sources of process sensitivity in implant and anneal processes -impact on yield
  

5. THE KEY CMOS PROBLEM: LEAKAGE AND POWER DISSIPATION. HOW CAN ELECTRICAL LEAKAGE BE REDUCED? HOW IS POWER MANAGEMENT ACCOMPLISHED?

Leakage and active power dissipation have become "show-stopping’ issues for further scaling of CMOS ICs. The challenge of device leakage and circuit power dissipation is so severe that design solutions at both the device and circuit level are required to effectively address the problem.

This section of the seminar describes the sources of device leakage and active power dissipation. It will discuss the most effective device and circuit level techniques that are employed at 45nm to mitigate the rapidly increasing device leakage and power dissipation problems.

• Primary source of device leakage: subthreshold, gate dielectric, & junction leakage
• Leakage suppression techniques – implications for process integration
• Active power dissipation issues: parasitic capacitance and resistance
• Power management techniques: multiple Vt devices, sleep mode devices, back-gate bias, multi-core processors - implications for process integration

The heart of a microchip is the transistor, and the key performance-limiting component of the transistor is the length of the gate electrode. Defining and consistently maintaining the critical dimension (CD) of this fundamental structure is the most challenging aspect of 45nm manufacturing.

This section of the seminar provides a detailed description of the feed forward/feed back manufacturing methodology required to maintain effective control of the polysilicon gate CD. The physical obstacles to effective CD control (193 resist line-edge roughness, etch chamber matching irregularities, top-down CD measurement, etc.) are discussed and quantified.

• The technical challenges in fabricating well-controlled 45nm gates
• The adverse impact of poly CD variations
• Identifying and controlling sources of polysilicon gate etch variation
• Using APC with in-line SEM measurement to optimize etch process and control polysilicon gate CD

7. STATE-OF-THE-ART ULTRA-SHALLOW JUNCTION FORMATION: NEW IMPLANT AND ANNEAL TECHNOLOGIES

Ion implantation and associated thermal processes have dramatically evolved to accommodate the ultra-shallow junction formation and polysilicon gate doping requirements for scaling CMOS transistors to the 45nm technology node. This has resulted in significant changes to both ion implantation and thermal processes and process equipment.

This section of the seminar will describe the key developments in ion implantation processing, associated thermal processing, and integration strategies that enable CMOS transistor structure scaling to the 45nm node. The course identifies the unit process, process equipment and process integration changes that have enabled this scaling. It will explain how these new ion implantation and thermal processes enable the desired device structures and electrical functions.

• New junction implant processes: PAI, co-implants, new species
• New junction implant technologies: plasma doping, high mass molecules
• New junction anneal technologies: Flash, laser
• New junction integration techniques
  

Next to the polysilicon gate electrode length dimension, the most important scaling lever in CMOS technology is the thickness of the gate dielectric. However, the inability of silicon dioxide to scale to dimensions thinner than 12Å has posed a seemingly insurmountable roadblock to enhancing transistor drive current via the time-established technique of gate oxide thickness scaling. In addition, ultra-thin silicon dioxide gate oxides exhibit excessive electrical leakage that results in high standby power consumption and imposes severe constraints on IC performance. The solution to this vexing scaling problem lies in the successful employment of gate dielectrics with a k-value that is substantially higher than that of silicon dioxide. Such dielectrics, when employed with metal gates of the appropriate type, are the key enabling technology required to scale to 45nm and beyond.

This section of the seminar discuss the problems associated with the development of High-k/metal gate technology, what the technology consists of, and why it works.

• The death of SiO2 gate dielectrics and the driving forces behind the move to Hi-k gate dielectrics
• Issues with Hi-k dielectrics – mobility degradation and the role of interfacial layers
• Fermi-level pinning and the purpose of metal gates
• Metal gate material selection issues and process integration choices

9. THE ROLE OF IMMERSION LITHOGRAPHY AT THE 45nm NODE

The most important, fundamentally enabling technology for implementation of 45nm node CMOS technology is a lithographic process capable of creating photoresist lines and spaces of appropriately small dimensions with adequate precision and reproducibility. Recently, immersion lithography technology has stepped into this role ahead of other alternatives for 45nm, however, not everyone will use immersion lithography at 45nm.

This section of the seminar will discuss the fundamental challenges and issues for 45nm lithography technology. It will describe the status and outlook and future development path for immersion lithography at 45nm and beyond. It will also describe and discuss the alternatives to immersion lithography that will be implemented at 45nm and beyond.

• Lithography challenges at 45nm and beyond
• Immersion lithography – status and outlook
• Alternatives to immersion lithography at 45nm and beyond
  

• Overview of 45nm Back End Of Line (BEOL) issues and yield vulnerabilities
• 45nm interconnect physical structure and electrical function
• Local vs. global interconnect structures
• Special considerations for scaled vias and contacts
• Effects of scaling on Cu resistance
• Low-k dielectric considerations and process integration issues
  
  

• How does strain work to improve carrier mobility and drive current?
• Sources of compressive and tensile uniaxial strain: nitride films, silicon lattice mismatch (etch with SiGe or SiC deposition/refill), STI & salicide process-induced strain, "memorization" strain
• Uniaxial strain integration techniques
• Channel orientation effects and hybrid orientation technology (HOT)

• Is 32nm the terminal point for classical (planar) CMOS and Moore’s law?
• Nanoscale effects and their growing impact on CMOS manufacturing
• Lithography technology for 32nm
• 32nm device design & manufacturing issues and probable solutions

The Course Instructors:

The best instructors in the business will be teaching this course. Both instructors are world-class experts in their field, with over five decades of combined, hands-on industry experience. However, the instructors will add value to your seminar experience not only through their broad and deep technical expertise, but also through their ability to present complex technical information in a clear and engaging manner. Both of these instructors are highly experienced, skilled public speakers; this is essential for effective learning in an intensive information transfer environment such as this seminar.

Furthermore, the high quality, full-color seminar lecture notes provided by the instructors are profusely illustrated with clear, relevant graphics. The instructors efficiently communicate the material using intuitive visual illustrations linked to relevant physics equations, supported by state-of-the-art 2D & 3D graphics and numerous SEM and TEM photographs of real-world, leading-edge CMOS device structures. Key references are provided for independent follow-up study.

Your attendance at this seminar will provide you with a clear understanding of the key enabling technologies that are making 45nm technology a reality.

Jerry Healey

JERRY HEALEY BIOGRAPHY

Jerry Healey has been a technical professional in the semiconductor industry for 20 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Sematech Advanced Technology Development Facility, where he worked on advanced technology node development.

He is a renowned lecturer in the field of silicon processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, embedded non-volatile memory processing, and mixed signal devices. His audiences

remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful color graphics he uses to illustrate his lectures.

An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 10 years. He has also co-authored over 20 papers in the field of silicon processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.

"Jerry Healey is a superb public speaker who has a knack for making complex technical subjects clear and understandable." – J. Blume, AMD

Robert Simonton

ROBERT SIMONTON BIOGRAPHY

Robert Simonton is a world-recognized authority in the subjects of ion implantation process technology, rapid thermal processing, and leading-edge front-end-of-line (FEOL) process integration. He has remarkable experience in the semiconductor industry, with over thirty years as a semiconductor technology professional. His experience has afforded him the opportunity to develop a remarkably broad and deep understanding of leading-edge semiconductor processing issues.

Before 2000, Mr. Simonton has held a variety of senior product engineering, advanced product/process development, strategic/product marketing, and technology management positions with market-leading semiconductor process equipment companies, such as Varian and Eaton. In 2000, Mr. Simonton founded Simonton Associates, a consulting firm that specializes in resolving high-level technology and management issues for leading semiconductor process equipment suppliers. His consulting activities keep him in close touch with the key challenges for leading-edge fabrication processes and equipment at each new technology node.

Mr. Simonton has authored and co-authored over 40 technical papers and four book chapters on semiconductor process technology, and is the recipient of the SRC Outstanding Industrial Mentor Award. He has been a popular lecturer in the field of advanced silicon processing for over 15 years; he has been an instructor for UC Berkeley Extension (College of Engineering), Elsevier Europe Engineering Extension, the International Ion Implantation Technology Conference School, and Motorola University. His audiences remember him best for his technical depth, his broad industry experience, and his engaging, high-energy lecture style.

"Mr. Simonton is a walking encyclopedia of information regarding semiconductor processing issues. His knowledge is both current and leading edge. I enjoyed his talk immensely." – T. Jamison, Intel